
library IEEE;
use IEEE.std_logic_1164.all;

entity display_string is
	port (	clk			: in	std_logic;	
		reset			: in	std_logic;
		
		msg		: in string( 4 downto 1);

		display_data	: out	std_logic_vector (7 downto 0);
		display_enable	: out	std_logic_vector (3 downto 0)
	);
end entity display_string;


architecture structural of display_string is

	component display_char is
	port (	clk			: in	std_logic;	
		reset			: in	std_logic;
		
		char0		: in character;
		char1		: in character;
		char2		: in character;
		char3		: in character;

		display_data	: out	std_logic_vector (7 downto 0);
		display_enable	: out	std_logic_vector (3 downto 0)
	);
  end component display_char;
begin

lblctrl:	display_char port map (	clk			=> clk,	
					reset			=> reset,
					char0 => msg(4),
					char1 => msg(3),
					char2 => msg(2),
					char3 => msg(1),
					display_data	=> display_data,
					display_enable		=> display_enable
			);

end architecture structural;